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chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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Kythe: document how to index SystemVerilog code with Kythe & Verible #396

Closed ivan444 closed 4 years ago

ivan444 commented 4 years ago

Write a tutorial (or a script) with end-to-end flow for indexing SystemVerilog code using Verible & Kythe. Serve the references using Kythe's built in http server.

Umbrella issue: #185

fangism commented 4 years ago

Documentation is in README.md (front page)