chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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want space before open-brace of enum #404

Closed fangism closed 4 years ago

fangism commented 4 years ago

See first line:

Want:

typedef enum uint8_t {
  kFoo,
  kBar
} foo_t;

Got:

typedef enum uint8_t{
  kFoo,
  kBar
} foo_t;

Fix needs to add a case here:

https://github.com/google/verible/blob/0a331418dd3ba7cd8c98a8436f380638f0aeac91/verilog/formatting/token_annotator.cc#L336

by checking for context being immediately inside an enum.

fangism commented 4 years ago

b/164302106