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chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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[kythe] linkify macro definitions' use of macro formal arguments #595

Open fangism opened 3 years ago

fangism commented 3 years ago

Input test case

Try to reduce the test down to a single demonstrative file.

`define uvm_create_comp(_type_name_, _inst_name_) \
  _inst_name_ = _type_name_::type_id::create(`"_inst_name_`", this);

Describe what is wrong or missing

Formal arguments are _type_name_ and _inst_name_. Inside the definition body, only linkify those, because other names cannot be resolved without macro call-site context.

You will need to recursively lex the macro definition body.

MinaToma commented 3 years ago

Maybe a duplicate of this one: #425 @fangism feel free to close one of them.

fangism commented 3 years ago

Maybe a duplicate of this one: #425 @fangism feel free to close one of them.

This one is slightly different, it is only about formal arguments.

fangism commented 3 years ago

Note that references to macro formal arguments look like SymbolIdentifier and EvalStringLiteral when recursively lexing inside macro definition bodies.