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chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.
https://f4pga.org
Apache License 2.0
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ERROR: set_property IO_LOC_PAIRS: Incorrect number of arguments. #138

Open Talha-Ahmed-1 opened 3 years ago

Talha-Ahmed-1 commented 3 years ago

Can anyone figure out this.

TARGET="arty_35" make -C fpga
make[1]: Entering directory '/home/tahmed/TalhaUpdated/picofoxy/fpga'
cd build/arty_35 && symbiflow_synth -t Picofoxy -v /home/tahmed/TalhaUpdated/picofoxy/fpga/Picofoxy.v /home/tahmed/TalhaUpdated/picofoxy/fpga/PLL_8MHz.v /home/tahmed/TalhaUpdated/picofoxy/fpga/clk_wiz_0_clk_wiz.v   -d artix7 -p xc7a35tcsg324-1 -x ~/picofoxy/fpga/arty.xdc 2>&1 > /dev/null
ERROR: set_property IO_LOC_PAIRS: Incorrect number of arguments.
make[1]: *** [Makefile:53: build/arty_35/Picofoxy.eblif] Error 1
make[1]: Leaving directory '/home/tahmed/TalhaUpdated/picofoxy/fpga'
make: *** [Makefile:22: bitstream] Error 2
kgugala commented 3 years ago

hi @Talha-Ahmed-1 can you link to the design you're trying to build?

Talha-Ahmed-1 commented 3 years ago

I am following this repo: https://github.com/Talha-Ahmed-1/picofoxy My design resources are in this directory: https://github.com/Talha-Ahmed-1/picofoxy/tree/main/fpga

GitHub
GitHub - Talha-Ahmed-1/picofoxy: Pipelined In-order Core for Artix-7 Arty-35T board
Pipelined In-order Core for Artix-7 Arty-35T board - GitHub - Talha-Ahmed-1/picofoxy: Pipelined In-order Core for Artix-7 Arty-35T board