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chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.
https://f4pga.org
Apache License 2.0
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systemverilog-plugin: convert memory when accessing slice #458

Closed kamilrakoczy closed 1 year ago

kamilrakoczy commented 1 year ago

Fixes: https://github.com/antmicro/yosys-systemverilog/issues/1505

Convert memories to list of registers if we are accessing slice of memory.

yosys-systemverilog run: https://github.com/antmicro/yosys-systemverilog/actions/runs/4204594665 UHDM-integration test: https://github.com/chipsalliance/UHDM-integration-tests/pull/711