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chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.
https://f4pga.org
Apache License 2.0
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systemverilog-plugin: handle assignment pattern with only default inside cell port #460

Closed kamilrakoczy closed 1 year ago

kamilrakoczy commented 1 year ago

This PR adds support for assignment patters inside cell high conn port that is setting all values to come constant, e.g.:

mod  m (.data( '{default: '0} ));
kamilrakoczy commented 1 year ago

UHDM-integration-tests: https://github.com/chipsalliance/UHDM-integration-tests/pull/714

yosys-systemverilog run: https://github.com/antmicro/yosys-systemverilog/actions/runs/4281547440

kamilrakoczy commented 1 year ago

After: https://github.com/chipsalliance/Surelog/pull/3486 Surelog started to flattening such assignments, so this PR is no longer needed. Closing.