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chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.
https://f4pga.org
Apache License 2.0
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systemverilog-plugin: fix assignments on declaration #473

Closed kamilrakoczy closed 1 year ago

kamilrakoczy commented 1 year ago

This PR fixes assignments on declaration in more generic way. Assignments on declaration in genfor blocks are handled separately, so they are left intact.

UHDM-integration-tests: https://github.com/chipsalliance/UHDM-integration-tests/pull/719 yosys-systemverilog run: https://github.com/antmicro/yosys-systemverilog/actions/runs/4531860494

kamilrakoczy commented 1 year ago

Previous yosys-systemverilog run discovered, that opentitan synthesis failed with this change. It was due to additional children in AST_IDENTIFIER that was leftover after transforming it from AST_WIRE. I've fixed this.

new yosys-systemverilog run: https://github.com/antmicro/yosys-systemverilog/actions/runs/4598266847