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chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.
https://f4pga.org
Apache License 2.0
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systemverilog-plugin: fix size of struct used as I/O wire #479

Closed kamilrakoczy closed 1 year ago

kamilrakoczy commented 1 year ago

This PR contains multiple small fixes that combined fixes size of struct that is used as I/O in module.

UHDM-integration-tests: https://github.com/chipsalliance/UHDM-integration-tests/pull/720 yosys-systemverilog run: https://github.com/antmicro/yosys-systemverilog/actions/runs/4618618727