sv-plugin: Strip the node name using parent name instead of "."

[mandrys]

Considering the fact that the name can consist of escaped characters, including dot, we need to change the way of stripping the name of a node - instead of a dot, we now use the ancestor name.

Added test: https://github.com/chipsalliance/UHDM-integration-tests/pull/730 (It fails formal verification because of sv2v being unable to handle escaped characters, but is useful as a parsing test.)

Test yosys-systemverilog CI run: https://github.com/antmicro/yosys-systemverilog/actions/runs/4916684728.

[wsipak]

We've had an offline discussion about the vpi_handles and the other API of UHDM that allows dealing with objects, that we could consider here. I think using the UHDM::BaseClass -based stuff could also help us keep the code cleaner.

[mandrys]

New yosys-systemverilog run: https://github.com/antmicro/yosys-systemverilog/actions/runs/5134240233.

[mandrys]

New yosys-systemverilog run: https://github.com/antmicro/yosys-systemverilog/actions/runs/5134720743.

[mandrys]

Latest yosys-systemverilog run passed, only formal verification failed for some unexpected passes: https://github.com/antmicro/yosys-systemverilog/actions/runs/5134720743/jobs/9239550297. When the PR is approved, I'll squash the commits with fixes and merge it.