systemverilog-plugin: Enable non-synthesizable code removal in Surelog.

[mglb]

Always activate -synth option in Surelog, which makes it ignore code between // synopsys translate_off and // synopsys translate_on (and a few other similar comments).

yosys-systemverilog: https://github.com/antmicro/yosys-systemverilog/actions/runs/4959300348

[mglb]

yosys-systemverilog CI failed when building opentitan with this branch. I've rebased and check it again. Draft until everything end up green.

[mglb]

False alarm, seems to work fine: https://github.com/antmicro/yosys-systemverilog/actions/runs/4959300348