antmicro/yosys-systemverilog#1743: Compensate for chipsalliance/Surelog#3670

[hs-apotell]

antmicro/yosys-systemverilog#1743: Compensate for chipsalliance/Surelog#3670

UHDM model hierarchy changed to enforce vpiParent as weak reference.

[mglb]

I did run the PR + https://github.com/chipsalliance/Surelog/pull/3670 in yosys-systemverilog CI, many tests fail: https://github.com/antmicro/yosys-systemverilog/actions/runs/5121636527 I'll look into the Surelog/UHDM change soon to see what should be done in the plugin.

[hs-apotell]

I ran the CI pipeline in Surelog repository and the build passed. https://github.com/chipsalliance/Surelog/pull/3681 Happy to assist in anyway possible.

The UHDM/Surelog change should have minimal impact outside the core implementation itself.

[hs-apotell]

@mglb Any update on this PR? Anything I can do to bump up the priority on this?

[mglb]

@hs-apotell Turns out the plugin doesn't work with Surelog's master, which is responsible for at least some issues from the yosys-systemverilog CI run linked above. It would be best to wait until we catch up with the master branch - this work is already in progress.

[hs-apotell]

@hs-apotell Turns out the plugin doesn't work with Surelog's master, which is responsible for at least some issues from the yosys-systemverilog CI run linked above. It would be best to wait until we catch up with the master branch - this work is already in progress.

Appreciate the update. Let me know when you are ready to try out this change again and I can rebase the Surelog PR.

[mglb]

@hs-apotell FYI: you can fork yosys-systemverilog, change submodule revisions/remotes to point to your changes, commit+push, and create a Draft PR. The CI will test it using code from revisions/forks configured on your branch.

Instructions how to change submodule can be found in the readme: https://github.com/antmicro/yosys-systemverilog#using-dedicated-branch

[hs-apotell]

Are the issues reported against Surelog master resolved?

[mglb]

Every related issue reported against Surelog/UHDM has been fixed AFAIK. With https://github.com/chipsalliance/yosys-f4pga-plugins/pull/528 merged, only one test in yosys-systemverilog fails with Surelog master.

[hs-apotell]

@mglb I forked the yosys-systemverilog repository and attempted a build it never gets executed. I have 3 builds waiting in the queue for over 10 hours. https://github.com/Apotell/yosys-systemverilog/actions

Am I missing some required permissions for the self-hosted runners?

[pgielda]

Custom runners are "private" to an org. In principle the only way for them to run for external users is to open a PR to that org (so in this case to https://github.com/antmicro/yosys-systemverilog). You cannot use them "privately" (unless you set up exactly the same "private" infrastructure)