systemverilog-plugin: fix anonymous enum when declared in submodules

[kamilrakoczy]

This PR fixes anonymous enums when they are declared in submodule and this submodule is used multiple times with the same parameters.

UHDM-integration-test: https://github.com/chipsalliance/UHDM-integration-tests/pull/739 yosys-systemverilog run: https://github.com/antmicro/yosys-systemverilog/actions/runs/5130641235

All unexpected failures in yosys-systemverilog run:

yosys:asicworld/code_hdl_models_GrayCounter.v
yosys:simple/always03.v
yosys:simple/sincos.v
yosys:asicworld/code_verilog_tutorial_fsm_full.v
yosys:simple/operators.v

are due to additional IdString and different optimizations applied to netlist. I've checked that AST for this tests are identical as before this PR.

[kamilrakoczy]

New yosys-systemverilog run: https://github.com/antmicro/yosys-systemverilog/actions/runs/5176458076