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chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.
https://f4pga.org
Apache License 2.0
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systemverilog-plugin: fix convert_range function #533

Closed kamilrakoczy closed 11 months ago

kamilrakoczy commented 1 year ago

This fixes multiranges for wires that doesn't start with 0.

yosys-systemverilog run: https://github.com/antmicro/yosys-systemverilog/actions/runs/5310972213 UHDM-integration-tests: https://github.com/chipsalliance/UHDM-integration-tests/pull/745, https://github.com/chipsalliance/UHDM-integration-tests/pull/744

All failing formal verification tests in yosys-systemverilog are false-negative. I've verified that they produce the same AST:

UHDM-integration-tests:MultiAssignmentPatternOfConcat/top.sv
UHDM-integration-tests:MemoryPort/top.sv
mglb commented 11 months ago

PR moved to Synlig repository: https://github.com/chipsalliance/synlig/pull/2072