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chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.
https://f4pga.org
Apache License 2.0
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Not supported SystemVerilog bit vector functions #548

Open iv2nl0b9v opened 5 months ago

iv2nl0b9v commented 5 months ago

Repro

module count_ones (
  input  logic [4:0] in,
  output logic [4:0] out
);
assign out = $countones(in);
endmodule : count_ones

UHDM converter doesn't seem to support SV bit vector functions: https://circuitcove.com/system-tasks-vector/ Not sure if it's intended.

kgugala commented 5 months ago

hi @iv2nl0b9v the systemverilog plugin has been moved to https://github.com/chipsalliance/synlig repository. Can you check if the issue you're reporting is present there? If, please report this problem there