Not supported while loop

[iv2nl0b9v]

While loop not supported for synthesizeable code:

module while_loop(
  input logic [3:0] in,
  output logic [3:0] out
);
  always @(in) begin
    integer a = 3;
    while (a >= 0) begin
      out[a] = in[a];
      a = a - 1;
    end
  end
endmodule : while_loop