Open acomodi opened 3 years ago
@acomodi So the current behavior is expected as the clock parameters (period, waveform) on the BUFGs are the same as on the PLL output wires that are driving them. So what you expect is the following SDC:
create_clock -period 16.6667 -waveform {0 8.33333} crg_clkout0
create_clock -period 16.6667 -waveform {0 8.33333} crg_clkout_buf0
create_clock -period 5 -waveform {0 2.5} crg_clkout3
create_clock -period 5 -waveform {0 2.5} crg_clkout_buf3
create_clock -period 40 -waveform {0 20} crg_clkout4
create_clock -period 40 -waveform {0 20} crg_clkout_buf4
Of course what is worrying is the fact that the clocks for crg_clkout1 and crg_clkout2 so CLKOUT1 and CLKOUT2 outputs of the PLL are not in the SDC. Is the SDC you pasted complete?
Of course what is worrying is the fact that the clocks for crg_clkout1 and crg_clkout2 so CLKOUT1 and CLKOUT2 outputs of the PLL are not in the SDC. Is the SDC you pasted complete?
@tmichalak Those are absent as the test is the minilitex one, wihtout DDR and Ethernet. Yosys prunes away the BUFG related to CLKOUT1 and CLKOUT2, and the SDC plugin discards those nets and does not output them in the final SDC, so that SDC is complete indeed.
What is missing though is also the CLKIN to the PLL which I am not sure why was not added.
You mean CLKIN1
? Well, it's driven by some explicitly added clock thus is itself neither an explicit (added by create_clock) or generated (propagated from the explicitly added clock wire but with different clock parameters).
Poke?
What is the status here?
@acomodi from my perspective the current behavior is expected. So adding this exception would be VPR specific. @litghost thoughts?
The main issue comes from the fact that VPR is not able to propagate the clocks. In fact, this is what results when running in VPR:
160 # Build Timing Graph took 0.04 seconds (max_rss 176.2 MiB, delta_rss +0.0 MiB)
161 Netlist contains 8 clocks
162 Netlist Clock 'crg_clkin' Fanout: 9 pins (0.0%), 9 blocks (0.1%)
163 Netlist Clock 'sys_clk' Fanout: 2125 pins (4.3%), 2092 blocks (20.2%)
164 Netlist Clock 'idelay_clk' Fanout: 8 pins (0.0%), 8 blocks (0.1%)
165 Netlist Clock 'eth_clk' Fanout: 1 pins (0.0%), 1 blocks (0.0%)
166 Netlist Clock 'pll_fb' Fanout: 1 pins (0.0%), 1 blocks (0.0%)
167 Netlist Clock 'crg_clkout0' Fanout: 1 pins (0.0%), 1 blocks (0.0%)
168 Netlist Clock 'crg_clkout3' Fanout: 1 pins (0.0%), 1 blocks (0.0%)
169 Netlist Clock 'crg_clkout4' Fanout: 1 pins (0.0%), 1 blocks (0.0%)
170 # Load Timing Constraints
171
172 Applied 3 SDC commands from '/data/symbiflow/symbiflow-arch-defs/build/xc/xc7/tests/soc/litex/mini/minilitex_arty/artix7-xc7a50t-virt-xc7a50t-test/top_synth.sdc'
173 Timing constraints created 3 clocks
174 Constrained Clock 'crg_clkout0' Source: 'PLLE2_ADV.CLKOUT0[0]'
175 Constrained Clock 'crg_clkout3' Source: 'PLLE2_ADV.CLKOUT3[0]'
176 Constrained Clock 'crg_clkout4' Source: 'PLLE2_ADV.CLKOUT4[0]'
The only constrained nets are the PLL clock output nets.
If the SDC lacks sys_clk
, the entire logic of the LiteX core will be unconstrained at the moment.
I think that, for the time being we should output the SDC relative to all the clcock different clock netlists that are outputs of clock tiles (namely, BUFG, PLL, etc.).
As a longer term solution we might need to add capabilities in VPR to understand that a clock net that, for instance, passes through a BUFG, has the same constraint as the PLL output.
In this case sys_clk
will have the same constraint applied to crg_clkout0
applied.
So I believe the fixes in #54 are good, but we do need a "verbose" SDC output for VPR. So make write_sdc
have a -include_propigated_clock
option, and we use that for VPR?'
@acomodi / @tmichalak I believe that this would resolve the issue?
@acomodi @litghost Adding a switch will work.
@tmichalak - Yes, we most certainly want to be able to write a SDC file with all clocks propagated, that was one of the points of pulling the data into Yosys in the first place...
@acomodi @litghost @mithro I created a PR with the include_propagated_clocks
switch: #65
With the clock propagation enhancements done in https://github.com/SymbiFlow/yosys-symbiflow-plugins/pull/54, the resulting SDC does not take into account the output clock from BUFGs connected to the PLL outputs.
This causes VPR to not correctly constrain clock signals, resulting in higher run-time and an
nan
CPD, such as in the following example:Resulting SDC:
This example is taken from the LiteX mini design, for which the
crg_clkout1
andcrg_clkout2
clock nets are unconnected, therefore they do not end up in the SDC, and this is expected.The problem though is that the correct SDC for VPR should have also the
crg_clkoutN_bufN
clocks as well. I notice also that the clock constraint for the input clock net to the PLL is missing as well.