The ref_sub module output generate only 2 results rather than 5 (5 banks)

[chongxi]

[chongxi]

Although latency=5 and interval=6 estimation is correct

[chongxi]

Turns out axi-stream input can only take 1 registered input, plus 1+ input, that is two inputs. If the module cannot output as fast as next input arrives, we lost data.

To solve that, a FWFT (first-word-fall-through) FIFO is required and should be connected as follows:

  fifo_160_to_160 fifo_to_ref_sub (
    .clk  (clk                      ), // input wire clk
    .srst (rst                      ), // input wire srst
    .din  (mua_stream_V_data_V_din  ), // input wire [159 : 0] din
    .wr_en(mua_stream_V_valid       ), // input wire wr_en
    .rd_en(mua_stream_V_data_V_read ), // input wire rd_en
    .dout (mua_stream_V_data_V_dout ), // output wire [159 : 0] dout
    .full (mua_stream_V_data_V_full ), // output wire full
    .empty(mua_stream_V_data_V_empty)  // output wire empty
  );

  ref_sub_0 ref_sub (
    .ap_clk                     (clk                        ), // input wire ap_clk
    .ap_rst_n                   (!rst                       ), // input wire ap_rst_n
    .mua_stream_V_data_V_dout   (mua_stream_V_data_V_dout   ), // input wire [159 : 0] mua_stream_V_data_V_dout
    .mua_stream_V_data_V_empty_n(!mua_stream_V_data_V_empty ), // input wire mua_stream_V_data_V_empty_n
    .mua_stream_V_data_V_read   (mua_stream_V_data_V_read   ), // output wire mua_stream_V_data_V_read
    .muar_stream_V_data_V_TVALID(muar_stream_V_data_V_TVALID), // output wire muar_stream_V_data_V_TVALID
    .muar_stream_V_data_V_TREADY(muar_stream_V_data_V_TREADY), // input wire muar_stream_V_data_V_TREADY
    .muar_stream_V_data_V_TDATA (muar_stream_V_data_V_TDATA )  // output wire [159 : 0] muar_stream_V_data_V_TDATA
  );

By doing this, the testing results:

Watch the mua_stream_V_data_V_read (5 times) which is the read signal to the FIFO, and because it is a FWFT FIFO the data output at the same clock as the read signal. The interval of the read signal is 6, which is the processing interval of ref_sub module.

[chongxi]

The muar signals are the final output, which is also interval at 6 clocks. The subtraction module starts to take new input and generate output from the second frame.

The latency from the first input to the first output is 5 (from read to valid), while the interval from first input to the second input is 6 (from read to read):