Open chongxi opened 2 years ago
from spiketag.fpga.memory_api import read_mem_16
import time
sync = []
while True:
sync.append(read_mem_16(0))
time.sleep(0.01)
After start recording, stop the software sync recording loop and then plot the result:
The second duration is exactly twice length of the first duration.
Now it is possible to read the sync_pulse out of the FPGA using
spiketag.fpga.memory_api.read_mem_16
FPGA sync pulse: