Bandgap cell

[Ahmedredamohamed2022]

Hello, I hope my message finds you well. I am writing to you because i got an error when simulating the bandgap as shown. Here, I want to describe what i did 1-I generated bandgap_lvs.spice from bandgap.gds 2- I used bandgap_tb_tc.spice with bandgap_lvs.spice 3- I opened a terminal and wrote ngspice bandgap_tb_tc.spice and found the shown error. can you help me to fix this error. bandgap_lvs.spice , bandgap.gds, and bandgap_tb_tc.spice are attached in the next link https://github.com/Ahmedredamohamed2022/Manual_Lab

[christoph-weiser]

You missed to include the subckt definition of the pnp device. I think the required file from the pdk is found in models/all.spice

[Ahmedredamohamed2022]

I would like to inform you that, i simulated the schematic circuit successfully. However, when I generated the bandgap_lvs.spice from the layout and re-simulate the testbench again , i found this error. Is there any other file should i add to simulate the bandgap_lvs.spice !

[christoph-weiser]

Ok. In that case I think I know what is going on. The tool will extract a circuit that is different than the one in the PDK. . So check what pins the pnp device has in the PDK. Then check how the device is extracted with magic. There is even a tutorial on youtube on this topic. I also made a script to fix this problem you find it in my ic_tools repo.

[Ahmedredamohamed2022]

yeah, I got it. Thank you for your patience Here, I simulated the extracted spice from the layout and adjust the pnp terminals. However, I get a difference between the pre-layout and post layout simulation. Does it mean the extracted spice file is not correct. Extracted spice file is attached here https://github.com/Ahmedredamohamed2022/Manual_Lab

[Ahmedredamohamed2022]

Hi, I found why the simulation result of extracted spice is not matched with the post-layout simulation result. When doing LVS check , the Netlists do not match, as shown. Do you think there is a wire in the layout is not connected as a schematic, right! or i do not have the last version of the layout.

[Ahmedredamohamed2022]

[Ahmedredamohamed2022]

[Ahmedredamohamed2022]

[Ahmedredamohamed2022]

both gates have the same label/port! is it right!!

[christoph-weiser]

Yes you are right. You can open the layout one level up in the hierarchy to see, which pin is which, since the naming is correct there. I don't see the issue, because remove labels of subblocks before I run lvs.

[Ahmedredamohamed2022]

Is there a way to remove labels of subblocks to run lvs! please

[christoph-weiser]

Yes in my ic_tools package you find a script called "assemble". It builds on some of the other scripts in the repository and will do that. If you want to create your own custom setup i suggest looking at the "labelremove" and "labelextract" scripts also found in the repository.

[Ahmedredamohamed2022]

Thanks. Excuse me what does it mean this error!

[christoph-weiser]

The first picture tells you that in Circuit 1 two sky130_fd_pr__pnp_05v5 devices have a connection from vss to the second node of the subckt. In Circuit 2: here are also two connections from vss to the second node of the subckt. However there are also additional two connections from vss to the first node of the subckt.

The second picture then tells you that there are connetions found in one netlist that cannot be found in the other. It also states that this is regarding the first port of sky130_fd_pr__pnp_05v5. It assigns this net a automatic name called a_26_26.

These lvs errors can be difficult to debug, but it looks like you have shorted port 1 and port 2 in the circuit 2, which is not the case in circuit 1.

[Ahmedredamohamed2022]

yeah, I got it. Thank you for your guidance.