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chrysn / efm32gg-hal

Implementation of the `embedded-hal` traits for EFM32GG microcontrollers
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bit banding gpio on efm32hg #4

Open jacobrosenthal opened 5 years ago

jacobrosenthal commented 5 years ago

Im not sure why yet, but bit banding for efm32hg isnt working. I altered for outset and outclr https://github.com/jacobrosenthal/efm32gg-hal/commit/42008ea48af7236dd8a5e66fd089927be217bb33

And that worked so I know everything else is set up

Im not familiar with bit banding. Any ideas?

chrysn commented 5 years ago

The M0 devices don't support bit-banding.

There's two ways to atomically set the bits in the register; the original series-0 devices (at least EFM32GG) had set/clear registers, but the series-0 radio and newer (at least the M3/4 I've checked) don't have set/clear registers.

As long as I didn't run into anything that did not have bit banding, it was a simplification approach to always use bit-banding rather than cfg-switch between a bit-banding and a set/clr operation; given that we're past that point, we'll need the GPIO module to behave conditionally on the presence of bit-banding, and introduce an appropriate condition for that (cf. https://github.com/em32-rs/wg/issues/6). If there is any ambiguity, we should err on the side of using set/clr, as that'll fail to compile on devices that have no set/clr, while bit-banding would fail silently. (I do hope that SL had the wisdom not to produce any devices that support neither, for that'd mean that set/clear operations will require ownership of a complete GPIO bank, or a critical section).

chrysn commented 5 years ago

I've noticed that there is no atomic access in M0 either.

The way forward here is probably to introduce an internal _has_gpio_setclear feature (pulled in by M0 chips) and cfg-gate a set/clear and a bitbanded implementation of GPIO setting and clearing. (The inverse way would to have a _has_bitband feature, either'd work).

I'd be curious to compare the result quality (in terms of code size and execution time) of the two implementations on chips like EFM32GG that support both.