Still in progress as I'd still looking on how to have all the pin mode encoded as type. Currently looking if it's possible to follow stm32-rs hals approach.
It would be interesting to also implement each bank's ctrl config. A bit convoluted though, as it's only used for alternate config drive strength in efm32 series, while in efr32xg it used for both alternate and standard config, with each config has 3 registers: DISDIN, SLEWRATE, and DRIVESTRENGTH.
Also wondering if it would be more preferred to use into_<pinmode> nomenclature here, as already used in nrf-rs and stm32-rs.
Attempted to refactor gpio implementation together with @jacobrosenthal (https://github.com/fudanchii/imtomu-rs/pull/23).
Still in progress as I'd still looking on how to have all the pin mode encoded as type. Currently looking if it's possible to follow stm32-rs hals approach.
It would be interesting to also implement each bank's ctrl config. A bit convoluted though, as it's only used for alternate config drive strength in efm32 series, while in efr32xg it used for both alternate and standard config, with each config has 3 registers:
DISDIN,SLEWRATE, andDRIVESTRENGTH.Also wondering if it would be more preferred to use
into_<pinmode>nomenclature here, as already used in nrf-rs and stm32-rs.