atom_display_fpga リポジトリについての質問

[universemodifier]

拝啓、ご無事であることを願っております。 atom_display_fpga リポジトリに対する素晴らしい取り組みに感謝します。 Scala について多くのことを学ぶのに役立ちました。

現在、Nano PSRAM モジュールを備えた M5Atom ディスプレイ キットを入手しています。

FPGA の更新は M5GFX ライブラリ内で行われることがわかりましたが、それは ID に文字 H と D が含まれている場合に限られます。

アップデート方法についてアドバイスをいただけますか? または コードがすでにサポートしている場合、正しい設定についてアドバイスをいただけますか?

周波数をサポートするためにbase_ Clockを変更しようとしました。

ディスプレイのタイミングが異なるため、更新する必要があります。 今までディスプレイは同期しませんでした。

日本語は私の主な言語ではないので、翻訳者を使用しています。 翻訳ミスはご容赦ください。 主に英語を使います

ディスプレイに関する詳細は次のとおりです。

Dear Mr. I hope You are well. Thank You for the amazing work on the atom_display_fpga repository. It helped me to learn a lot about scala.

I have now an M5Atom Display kit with the Nano PSRAM module.

I did see that the updating of the FPGA is done inside the M5GFX Library but only if the ID includes the letters H and D.

Can You give me advice how to update ? OR If the code already supports it can you give me advice for correct settings ?

I did try to modify the base_clock to support the frequency.

I need to update because my display has different timings. Till now the Display does not sync.

Japanese is not my main language so i use a translator. Please excuse translation errors. Mainly i use english

Following are the details about the Display.

1080x1080 Round Display 5" Size

This are working settings for Raspberry PI hdmi_timings=1080 0 60 10 35 1080 0 10 4 2 0 0 0 60 0 77930000 0

I added this explanation here because it was hard to find hdmi_timings=

= horizontal pixels (width) = invert hsync polarity = horizontal forward padding from DE acitve edge = hsync pulse width in pixel clocks = vertical back padding from DE active edge = vertical pixels height (lines) = invert vsync polarity = vertical forward padding from DE active edge = vsync pulse width in pixel clocks = vertical back padding from DE active edge = leave at zero = leave at zero = leave at zero = screen refresh rate in Hz = leave at zero = clock frequency (width*height*framerate) = * This is EDID Information from Ubuntu 22.04 OS x86_64 Block 0, Base EDID: EDID Structure Version & Revision: 1.3 Vendor & Product Identification: Manufacturer: LZT Model: 1 Made in: week 12 of 2017 Basic Display Parameters & Features: Digital display Image size is variable Gamma: 2.20 RGB color display First detailed timing is the preferred timing Color Characteristics: Red : 0.6015, 0.3359 Green: 0.3056, 0.5263 Blue : 0.1513, 0.1201 White: 0.3134, 0.3291 Established Timings I & II: none Standard Timings: Detailed Timing Descriptors: DTD 1: 1080x1080 60.003 Hz 1:1 65.764 kHz 77.930 MHz (90 mm x 160 mm) Hfront 60 Hsync 10 Hback 35 Hpol N Vfront 10 Vsync 4 Vback 2 Vpol N Display Product Name: 'YongXing ' Display Product Serial Number: '00000000 ' Display Range Limits: Monitor ranges (GTF): 23-75 Hz V, 15-240 kHz H, max dotclock 340 MHz Extension blocks: 1 Checksum: 0x7c ---------------- Block 1, CTA-861 Extension Block: Revision: 3 Basic audio support Supports YCbCr 4:4:4 Supports YCbCr 4:2:2 Native detailed modes: 4 Video Data Block: Audio Data Block: Linear PCM: Max channels: 2 Supported sample rates (kHz): 192 176.4 96 88.2 48 44.1 32 Supported sample sizes (bits): 24 20 16 Vendor-Specific Data Block (HDMI), OUI 00-0C-03: Source physical address: 3.0.0.0 Supports_AI Detailed Timing Descriptors: DTD 2: 1080x1080 60.003 Hz 1:1 65.764 kHz 77.930 MHz (90 mm x 160 mm) Hfront 60 Hsync 10 Hback 35 Hpol N Vfront 10 Vsync 4 Vback 2 Vpol N DTD 3: 1080x1080 60.003 Hz 1:1 65.764 kHz 77.930 MHz (90 mm x 160 mm) Hfront 60 Hsync 10 Hback 35 Hpol N Vfront 10 Vsync 4 Vback 2 Vpol N DTD 4: 1080x1080 60.003 Hz 1:1 65.764 kHz 77.930 MHz (90 mm x 160 mm) Hfront 60 Hsync 10 Hback 35 Hpol N Vfront 10 Vsync 4 Vback 2 Vpol N DTD 5: 1080x1080 60.003 Hz 1:1 65.764 kHz 77.930 MHz (90 mm x 160 mm) Hfront 60 Hsync 10 Hback 35 Hpol N Vfront 10 Vsync 4 Vback 2 Vpol N DTD 6: 1080x1080 60.003 Hz 1:1 65.764 kHz 77.930 MHz (90 mm x 160 mm) Hfront 60 Hsync 10 Hback 35 Hpol N Vfront 10 Vsync 4 Vback 2 Vpol N Checksum: 0x8e

[ciniml]

ATOM Display can only handle up to a pixel clock of 74.25 MHz, so it is necessary to adjust video parameters in order to display at 1080x1080 60Hz.

e.g. total horizontal pixels = 1135 (active 1080 + blanking 55), total vertical pixels = 1090 (active 1080 + blanking 10), at pixel clock = 74.25[MHz] -> 74250000/(1135*1090) = 60.0169[Hz]

You can try it without modifying FPGA design. Just use M5AtomDisplay class like below:

M5AtomDisplay display ( 1080, 1080, 60 );

M5GFX automatically calculates feasible pixel clock and video timing parameters.

https://github.com/m5stack/M5GFX/blob/master/docs/ATOMDisplay.md

[universemodifier]

Thank You for the Answer. I did try before this already. Sadly it did not work. I enabled also ESP_LOGI and additional output in the Panel_M5HDMI.cpp so i see the calculated value. I would go modify the pixel clock in CLK_IN_74M25 and in the Gowin Ip generator. I did try to set to period 11.764 and waveform 0 5.882 so i have a bit head room. Also the base_clock in the Driver i did adjust to the value. ( 85 Mhz "85000000")

I can not confirm if the FPGA was updated. this is my biggest issue. My M5 HDMI reports [M5HDMI] FPGA ID:48440004

I dont see it triggers the FPGA Update in the init.

Please give me an advice.

I did manage to compile and get the bitstream. Only one warning for out of range of the pixel clock. i did not find yet the cause of the warning but i will find that.

Just how do i trigger the FPGA Update correctly.

[ciniml]

I did try before this already. Sadly it did not work. I enabled also ESP_LOGI and additional output in the Panel_M5HDMI.cpp so i see the calculated value.

What is the problem with changing the parameters of M5GFX? Is it because the display does not support the video parameters calculated by M5GFX automatically? If so, would it be resolved if you could set the manually calculated parameters?

I would go modify the pixel clock in CLK_IN_74M25 and in the Gowin Ip generator. I did try to set to period 11.764 and waveform 0 5.882 so i have a bit head room. Also the base_clock in the Driver i did adjust to the value. ( 85 Mhz "85000000")

As previously mentioned, ATOM Display does not support a pixel clock higher than 74.25 MHz. This is not an easy design change but rather a performance limitation of the FPGA itself.

Due to the complexity of the FPGA in current ATOM Display devices, the maximum operating frequency for processing video signals is capped at 74.25 MHz. Therefore, in order to directly support an 85 MHz pixel clock, adjustments must be made to increase the operating frequency of the FPGA design.

I can not confirm if the FPGA was updated. this is my biggest issue. My M5 HDMI reports [M5HDMI] FPGA ID:48440004

How did you try to update the design?

The build script for the test firmware in this repository automatically embeds the updated FPGA design into the firmware. Please note that reconfiguration of the FPGA can only be performed after power-up, meaning ATOM Display must be power-cycled to perform reconfiguration of the FPGA. Just resetting the ATOM Display is not enough to reconfigure the FPGA.

This constraint is inherent to ATOM Display's hardware specifications (There are no connections from ESP32 to FPGA RECONFIG_N signal to force reconfiguration.)

https://github.com/ciniml/atom_display_fpga/tree/main/test

[universemodifier]

I did use the test program to test and update the FPGA.

Also i did try powercycle the FPGA and also the ESP. I am not sure if it really is doing it. so i did comment out the search for "H" and "D" Now its running the SRAM update but i am not sure if its actually doing it.

I got it syncing now but i did run in an another bug somehow.

The X axis has duplicated pixels now. so effective i have now a 540 by 1080 Display. ( 540 width ) It runs and displays stuff but in x axis everything is doubled. ( A square 10 x 10 ends up as 20x10) I tried to play around with scalings in different versions but it did not work.

This is my settings string which got the Display working for now. M5AtomDisplay display(1080, 1080, 30, 1080, 1080, 0, 0, 93360000U);

Yes the frequency is odd but it puts out juuuust enough ( 76,9 MHz ) so the display syncs. I can not measure exactly because my scope does not properly work above 60 MHZ.

[universemodifier]

Update: With display(540, 540, 60, 1080, 1080, 0, 2,93360000U); There is no pixel duplication anymore. I use that for now