Question about RISC-V designs

[SaltyfishK423]

Hello！ I recently read your paper, you used 6 open source RISC-V designs to generate data. I want to know what open source data you used, can you give me a download link?

[apri0426]

Sure, it is pulpino. There are originally 3 designs, pulpino configured with RISCY core, pulpino configured with RISCY core and floating point extension, pulpino configured with zero-riscy core. And we implement a hierarchical flow on these 3 designs to transform some sub modules into IPs and regard them as another 3 designs. So that adds up to 6 designs.

[SaltyfishK423]

Ok, thank you. When you carry out logical synthesis, do you directly use the rtl code in the RTL folder in the GitHub warehouse of pulpino, or do you need to download the whole pulpino project and carry out some operations before logical synthesis? I am not familiar with pulpino at present. I hope you can give me more instructions and suggestions.

[apri0426]

You need to run ./update-ips.py first to get all ips. Then the rtl files are in /rtl and /ips. This issue pulp-platform/pulpino#114 may contains useful information.

[RENEK-bool]

Hello, thank you very much for your work. At present, I am also trying to carry out logical synthesis of RISC-V design. I have read the issue you mentioned, and it seems that some replacement operations such as sp_ram_bank are still needed. But I don't quite understand how to operate it, because I just learned logic synthesis and am not familiar with it. Could you please tell me some details about your logical synthesis of the original design? Is it better to have a detailed process? In particular, I am curious about how to set the constraints required by logical synthesis. Are there relevant instructions in pulpino? Or if it is convenient for you, could you please provide the scripts used in the synthesis. @apri0426