Fixed a bug in parsing out-of-scope signals

cirosantilli / vcdvcd

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

Other

54 stars 21 forks source link

Fixed a bug in parsing out-of-scope signals #18

Closed christian-krieg closed 3 years ago

christian-krieg commented 3 years ago

When there are variables in the VCD file outside any scope, the current reference generation generates an empty module hierarchy, which results in a reference with a preceding period (e.g., ".sig1")
I added three lines to check whether the path is empty, and if it is, the signal name is added as reference, and "path + '.' + name" (original behavior) otherwise

cirosantilli commented 3 years ago

Thanks Christian, merged at: f92c125be60b183470420fe4a5b6817158c9694a

Consider adding a minimal tests next time around under test.py :) I made that easier now by allowing VCDVCD to be created from a string instead of path.