Adds signal slicing, scopes and regex based lookup

cirosantilli / vcdvcd

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

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Adds signal slicing, scopes and regex based lookup #19

Closed DanieleParravicini closed 3 years ago

cirosantilli commented 3 years ago

Thanks Daniele, can you add tests for the change to https://github.com/cirosantilli/vcdvcd/blob/master/test.py ?

DanieleParravicini commented 3 years ago

Sure, I will look into it!👍🏻

DanieleParravicini commented 3 years ago

I wrote some tests obtaining 78% coverage. Do you think it's enough?

Name	Stmts	Miss	Cover	Missing
test.py	86	1	99%	121
vcdvcd__init__.py	1	0	100%
vcdvcd\vcdvcd.py	245	53	78%	136, 156, 198-200, 219-221, 276, 282, 288, 294, 331, 336, 347, 350, 354, 363, 380, 383, 389, 440, 463-464, 472-490, 498-508, 520-523

cirosantilli commented 3 years ago

Thanks Daniele,

Don't worry too much about coverage, this is not a serious project for me, just to understand the goal of the PRs and keep things minimally working with a hello world of each case.

I've merged your changes and made the following changes:

tabs to spaces, remove trailing whitespace, chmx test.py :)
removed save_hierarchy as it is easy to do from caller
nonexistent signal with fixed string raises rather than returning an empty list

Let me know if any of those block you.

DanieleParravicini commented 3 years ago

Apart from tabs to spaces I agree ( just joking, lol ;) ). Have a great day!