Added support for single-line simulation command

cirosantilli / vcdvcd

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

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Added support for single-line simulation command #25

Closed christian-krieg closed 2 years ago

christian-krieg commented 2 years ago

PulseView generates VCD files with value changes on the same line as the time stamp, separated by white-space
Not sure if standard-compliant, but added support for it as GTKWave also supports it
Added a test to the testbench

DurandA commented 2 years ago

I think it would be cleaner to only include commit c15abc6 in the PR.

christian-krieg commented 2 years ago

Hi Arnaud,

I totally agree, I also tried doing so, but it's unclear to me how to achieve it... github includes all the other commits as well, although my master branch (from which I forked the feature branch) is up to date with upstream master.

If obvious to you how to resolve this, I am more than open for advice (: Probably thr most straight-forward solution would be to do a fresh clone, apply changes, file new PR ...

Cheers, Christian

christian-krieg commented 2 years ago

Did it following this answer on StackOverflow.

I close this PR to keep things clean :)

Cheerio, Christian

DurandA commented 2 years ago

Sorry for the late reply.

Another solution is to rebase:

git fetch upstream
git checkout feat/single-line-value-change
git rebase upstream/master
git push --force

You can also force push to the same branch instead of creating a new PR. It will replace all commits automatically.