cirosantilli / vcdvcd

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
Other
56 stars 21 forks source link

vcdcat misses an input signal #36

Open arunpatro opened 10 months ago

arunpatro commented 10 months ago

I have in my .vcd file, a variable called tb.clk. We can see it here like this ->

from vcdvcd import VCDVCD

vcd = VCDVCD('test/rotate100/wave.vcd')
print(vcd.references_to_ids.keys())
dict_keys(['tb.stim1.clk', 'tb.tb_mismatch', 'tb.clk', 'tb.load', 'tb.ena[1:0]', 'tb.data[99:0]', 'tb.q_ref[99:0]', 'tb.q_dut[99:0]'])

But when I do vcdcat test/rotate100/wave.vcd, I get a .txt file that is like this:

0 time
1 tb.data[99:0]
2 tb.ena[1:0]
3 tb.load
4 tb.q_dut[99:0]
5 tb.q_ref[99:0]
6 tb.stim1.clk
7 tb.tb_mismatch

0                         1 2 3                         4                         5 6 7 
=======================================================================================
0                         x x 1                         x                         x 0 0
5 4c0895e818484d609b1f05663 x 1                         x                         x 1 0
10 4c0895e818484d609b1f05663 x 1                         x                         x 0 0
15 d46df998db2c2846589375212 x 1 4c0895e818484d609b1f05663 4c0895e818484d609b1f05663 1 0
20 d

Why does it skip the tb.clk signal all together?

cirosantilli commented 10 months ago

Hi, can you provide a sample vcd to reproduce?