cirosantilli / vcdvcd

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
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print_dumps=True fails #5

Closed morrowsend closed 4 years ago

morrowsend commented 4 years ago

When I try to run the example it halts at line 52 and gives the following error:

VCDVCD(vcd_path, print_dumps=True)
  File "C:\Users\ALaptop\AppData\Roaming\Python\Python38\site-packages\vcdvcd\vcdvcd.py", line 121, in __init__
    print('{0:>{1}d} '.format(i, references_to_widths[ref]), end='')
ValueError: Precision not allowed in integer format specifier
cirosantilli commented 4 years ago

Thanks for the report,

I can't reproduce on Ubuntu 20.04, Python 3.8.2 or Python 2.7.18 with:

./vcdcat counter_tb.vcd

What's your python version and can you provide a reproduction example? This related thread did not help me much unfortunately: https://stackoverflow.com/questions/21200098/format-valueerror-precision-not-allowed-in-integer-format-specifier

morrowsend commented 4 years ago

I'm running a fresh install of Python 3.8.5 in Windows 10.

This happens with a VCD generated from GHDL of a very simple VHDL code I have my students write, but what is typical for multi-bit data. The code uses a counter to control a signal called sw_signal which is 4-bits wide and there are a 3-bit output bus called led_signal. One tells if the value on the sw is even, one led tells if it is odd, and one led tells if the value is a prime number.

Here's the files to test with.

from __future__ import print_function

import sys
from pprint import PrettyPrinter

from vcdvcd import VCDVCD

if (len(sys.argv) > 1):
    vcd_path = sys.argv[1]
else:
    vcd_path = 'top1.vcd'
pp = PrettyPrinter()

print('# get_data()')
vcd = VCDVCD(vcd_path)
pp.pprint(vcd.get_data())  # this works fine
print() 

print('# __init__(print_dumps=True)')
VCDVCD(vcd_path, print_dumps=True)  # this breaks
print()

VCD file named top1.vcd

$date
  Fri Jul 31 13:01:46 2020
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$scope module standard $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module numeric_std $end
$upscope $end
$scope module top_tb $end
$var reg 4 ! sw_signal[3:0] $end
$var reg 3 " led_signal[2:0] $end
$upscope $end
$enddefinitions $end
#0
b0000 !
b010 "
#10000000
b0001 !
b100 "
#20000000
b0010 !
b011 "
#30000000
b0011 !
b101 "
#40000000
b0100 !
b010 "
#50000000
b0101 !
b101 "
#60000000
b0110 !
b010 "
#70000000
b0111 !
b100 "
#80000000
b1000 !
b010 "
#90000000
b1001 !
b100 "
#100000000
b1010 !
b010 "
#110000000
b1011 !
b101 "
cirosantilli commented 4 years ago

I think this had been fixed at https://github.com/cirosantilli/vcdvcd/pull/4 on master, but I didn't release, pushed a release now in v1.0.6, let me know if it persists.

I like your educational efforts BTW, had a look at the website now.

morrowsend commented 4 years ago

Thanks! This fixed the issue on a couple of my examples I've tested so far. I rarely get a chance to write for my blog page, so I really appreciate the compliment too. Hopefully I'll have a post up in the next couple months showing how I'm using vcdvcd.

cirosantilli commented 4 years ago

Cool! Let me know about it when it comes out!