SystemVerilog 相关

[cisen]

https://github.com/dalance/sv-parser https://github.com/cisen/sourcecode-systemverilog-sv-parser

IEEE_Standard_1800-2012 SystemVerilog.pdf

ieee-standard-for-systemverilogunified-hardware-design-specifica2009.pdf

ieee-standard-for-systemverilogunified-hardware-design-specifica2017.pdf

IEEE_Standard_UVM_1800.2-2017.pdf

system_verilog_overview-ibm-symposium-johny_srouji.pdf

[cisen]

入门

• https://blog.csdn.net/weixin_46022434/category_9885145.html?spm=1001.2014.3001.5482

  数据类型

• https://blog.csdn.net/weixin_43830240/article/details/110587894
• https://zhaishuangdong.blog.csdn.net/article/details/105387646