Open cisen opened 2 years ago
如果usb2的话, 可以考虑study这个repo ip
https://github.com/lowRISC/opentitan/tree/master/hw/ip/usbdev
串行时钟速度 USB 2
USB4 (很复杂)
Gen 1 == Superspeed == SS
Gen 2 == Superspeed Plus == SSP
enjoy digital的usb3_pipe 很有意思
3.2 Gen 2x1 ssc (Spread Spectrum Clocking) 似乎是一个问题
如果usb2的话, 可以考虑study这个repo ip
https://github.com/lowRISC/opentitan/tree/master/hw/ip/usbdev
串行时钟速度 USB 2
- Low Speed 1.5 Mbps <- USB 1.1
- Full Speed 12 Mbps <- USB 1.1
- High Speed 480Mbps <- USB 2.0 USB 3
- Gen 1x1 5Gbps <- USB 3.0
- Gen 1x2 10Gbps <- USB 3.2 加上
- Gen 2x1 10Gbps <- USB 3.1 加上
- Gen 2x2 20Gbps <- USB 3.2 加上
USB4 (很复杂)
- Gen 3 - 20gbps
- Gen 3x2 - 40gbps
Gen 1 == Superspeed == SS Gen 2 == Superspeed Plus == SSP
enjoy digital的usb3_pipe 很有意思
3.2 Gen 2x1 ssc (Spread Spectrum Clocking) 似乎是一个问题
good, thx!
https://github.com/cisen/FPGA-USB-Device 好:https://github.com/cisen/usb_phy_verif https://github.com/WangXuan95/FPGA-ftdi245fifo https://github.com/ultraembedded/cores https://github.com/ulixxe/usb_cdc 依赖外部serde实现usb3:https://github.com/enjoy-digital/usb3_pipe https://github.com/avakar/usbcorev https://github.com/esynr3z/usb20dev https://github.com/circuitvalley/USB_C_Industrial_Camera_FPGA_USB3 https://github.com/cisen/usb_phy_verif rust: https://github.com/rust-embedded-community/usb-device
cdc : communication device class,CDC是通信设备级方案,是USB 转其他的接口的一类设备,比如USB转RS232,USB转Ethernet等 dfu : Device Firmware Upgrade 主要使用USB接口,实现固件的上传与下载 hid : humman interface device,人机接口级方案,多为不需要驱动的键盘鼠标等 msc: mass storage class,大容量存储方案,多为移动存储设备