Closed danielstumpp closed 2 years ago
The xilinx_u200_xdma_201830_2 devices we have are compatible with the 2020.2 examples. Specfically I am working off of this example repository: https://github.com/Xilinx/Vitis_Accel_Examples/tree/2020.2/host/p2p_bandwidth
Building this repository with Vitis 2020.2 creates the following error:
In file included from /ihome/ece2195_2022s/dcs98/RCDL/Vitis_Accel_Examples/common/includes/xcl2/xcl2.cpp:17:0:
/ihome/ece2195_2022s/dcs98/RCDL/Vitis_Accel_Examples/common/includes/xcl2/xcl2.cpp: In function ‘cl::Device xcl::find_device_bdf(const std::vector<cl::Device, std::allocator<cl::Device> >&, const string&)’:
/ihome/ece2195_2022s/dcs98/RCDL/Vitis_Accel_Examples/common/includes/xcl2/xcl2.cpp:71:49: error: ‘CL_DEVICE_PCIE_BDF’ was not declared in this scope
OCL_CHECK(err, err = devices[i].getInfo(CL_DEVICE_PCIE_BDF, &device_bdf));
^
/ihome/ece2195_2022s/dcs98/RCDL/Vitis_Accel_Examples/common/includes/xcl2/xcl2.hpp:27:5: note: in definition of macro ‘OCL_CHECK’
call; \
^
I had the same exact issue when I was setting up Vitis 2019 on Luke's computer. This means that the 2020.2 XRT isn't installed on viz. We have to bring this to kim wong
I had the same exact issue when I was setting up Vitis 2019 on Luke's computer. This means that the 2020.2 XRT isn't installed on viz. We have to bring this to kim wong
@cjg91 I tried it on fpga-n0 as well... not sure what that means then
https://support.xilinx.com/s/article/75253?language=en_US https://support.xilinx.com/s/question/0D52E00006hpXpXSAU/installation-of-multiple-versions-of-xrt?language=en_US
All CRC's nodes seem to use XRT for 2019.2. So it seems that we need to install XRT for 2020.2 in a different directory and set XILINX_XRT to that directory when we want to use Vitis 2020.2
Yes, I just came to that conclusion. No matter what version of Vitis being used XRT 2019.2 is always sourced.
The xilinx_u200_xdma_201830_2 devices we have are compatible with the 2020.2 examples. Specfically I am working off of this example repository: https://github.com/Xilinx/Vitis_Accel_Examples/tree/2020.2/host/p2p_bandwidth
I just noticed this. Why are you using that example? It's for p2p between NVME and FPGA. In the parent directory there's an fpga2fpga example that we want to characterize: https://github.com/Xilinx/Vitis_Accel_Examples/tree/2020.2/host/p2p_fpga2fpga
That was just the wrong link, the problem is the same I was using the fpga2fpga example. I also tested with just the hello world example and got the same error.
Completed and working
Tracking issues and progress for P2P characterization with CRC FPGAs
References used