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ckeh / vtr-verilog-to-routing

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What are the blif instances that are accepted by the VPR by default? #62

Closed GoogleCodeExporter closed 9 years ago

GoogleCodeExporter commented 9 years ago 
I would like to know the blif instances that are accepted by VPR inadditon to 
the conventional ones such as .names, .latch, .input,.output . I also would 
like to know on how to integrate vhdl models into xml architecture files for 
Hard blocks that I am currently facing diffficulties in doing.

Original issue reported on code.google.com by david.dh...@gmail.com on 25 Jun 2013 at 7:46

GoogleCodeExporter commented 9 years ago 
VPR can accept blackboxes.  In blif, this is of the format ".subckt 
[name_of_your_custom_block] [pin list]".  We provide examples of this in the 
vtr_flow/benchmarks folder and the vpr folder.

I don't understand what you mean by integrate VHDL models into xml architecture 
files.  If you mean how do you specify different hard blocks in the 
architecture file, then you should refer to both the VPR manual and to the 
examples that we provide in this wiki.

Original comment by JasonKai...@gmail.com on 25 Jun 2013 at 1:35

GoogleCodeExporter commented 9 years ago

Original comment by JasonKai...@gmail.com on 25 Jun 2013 at 1:35