Regarding the the special case that is invertible, but should not occur according to the assumption that target != current output. So far this case is handled as not invertible. This is just a suggestion to handle it as invertible.
REMU
This adds missing parenthesis and the case s == t => invertible
Summery of invertible, not invertible:
DIVU Lhs:
s = 0, t = ones => invertible, but should not happen as this means currently t = ones already
s = 0, t != ones => not invertible
t = ones, s != {0,1} => not invertible, overflow
DIVU Rhs:
t = s = 0 => invertible, but again should not happen
t = 0, s != ones => invertible
t = 0, s = ones => not invertible
t = ones, (s = ones) => invertible
t = ones, (s != ones) => invertible
DIVU
Regarding the the special case that is invertible, but should not occur according to the assumption that target != current output. So far this case is handled as not invertible. This is just a suggestion to handle it as invertible.
REMU
This adds missing parenthesis and the case s == t => invertible
Summery of invertible, not invertible:
DIVU Lhs: s = 0, t = ones => invertible, but should not happen as this means currently t = ones already s = 0, t != ones => not invertible t = ones, s != {0,1} => not invertible, overflow
DIVU Rhs: t = s = 0 => invertible, but again should not happen
t = 0, s != ones => invertible t = 0, s = ones => not invertible
t = ones, (s = ones) => invertible t = ones, (s != ones) => invertible
s < t => not invertible