clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler
https://clash-lang.org/
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Maintain variable names post-compilation #128

Closed ghost closed 4 years ago

ghost commented 8 years ago

I would really appreciate a feature to maintain variable naming post-compilation to VHDL or Verilog like MyHDL. As of now the code that clash outputs is very difficult to read or reason about its connection to the initial Haskell.

christiaanb commented 8 years ago

I'm currently working on fixing blockRam inference for Xilinx Vivado. Afterwards, I'll take a look at this.

christiaanb commented 8 years ago

I'm making progress on this. Some notes:

christiaanb commented 8 years ago

Some of the name-preservation improvements are part of the 0.6.11 release of CLaSH. I'll keep this issue open, as I'm sure we can do better than what's currently implemented.

christiaanb commented 4 years ago

Clash preserves most names these days; and when it doesn't you simply add a {-# NOINLINE xyz #-} pragma