clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler
https://clash-lang.org/
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Verilog `tbClockGen`: print nothing when clock stops #2519

Closed DigitalBrains1 closed 1 year ago

DigitalBrains1 commented 1 year ago

This ensures that Clash's testsuite doesn't trip up on simulation finish during normal operation. The testsuite assumes an error occured when VVP prints anything to stdout. This is needed for iverilog version 11 and later.

This commit was originally part of #2274 on master, but is needed in 1.6 as well.

(cherry picked from commit 07073588403ff39291447a68c7b0bf8891e10f53)

Still TODO: