Render `vioProbe` in own module

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

https://clash-lang.org/

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Render `vioProbe` in own module #2523

Closed martijnbastiaan closed 1 year ago

martijnbastiaan commented 1 year ago

Fixes #2500

Still TODO:

[X] ~~Write a changelog entry (see changelog/README.md)~~
[X] Check copyright notices are up to date in edited files
[x] Merge https://github.com/clash-lang/clash-compiler/pull/2511

DigitalBrains1 commented 1 year ago

Maybe add

-- See [Note: eta port names for trueDualPortBlockRam]
{-# OPTIONS_GHC -fno-do-lambda-eta-expansion #-}

martijnbastiaan commented 1 year ago

@christiaanb was pretty much against that last time around, but I don't remember the reasoning.

For this specific primitive: only clk will result in an HDL port name. The rest are blackbox-only arguments.

DigitalBrains1 commented 1 year ago

@christiaanb was pretty much against that last time around, but I don't remember the reasoning.

It was because in that case there was no need for the separate module. So you created a separate module specifically to get nice names. Here we do want a separate module for another reason. So we generate nice names for our separate module instead of a separate module for nice names. They're basically each other's reverse.

martijnbastiaan commented 1 year ago

Ok! Done!

martijnbastiaan commented 1 year ago

Thanks! Will set it to draft to make sure it doesn't get merged before https://github.com/clash-lang/clash-compiler/pull/2511.