Closed DigitalBrains1 closed 1 year ago
I'm not very fond of the name
seClockToDiffClock
. Why not justclockToDiffClock
? If that's not part of a release yet I'd prefer to change it. But then again, not really for this PR I suppose.
Now that we have two types Clock
and DiffClock
I can see how that makes sense. Before, it did not make sense. It would be saying you're turning a clock into a clock. You'd have needed to say what you're turning into what for it not to be nonsensical.
But now that the name can also refer to the type names instead of the concepts represented, I'm fine with changing it to that.
A new type is introduced to signify a differential clock signal that is passed to the design on two ports in antiphase. This is used by Xilinx
clockWizardDifferential
(note that Intel solves this case differently, so if we were to add an Intel primitive it would not need this type).With this new type, we prevent the creation of more
create_clock
statements in the global SDC file than is correct: only the positive phase of a differential pair should have acreate_clock
statement.Fixes #2518
Still TODO: