Wire up output probes correctly in VIO

[martijnbastiaan]

Fixes #2506

---

Example mentioned in issue now looks like:

/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.
** GENERATED BY CLASH 1.7.0. DO NOT MODIFY.
*/
`default_nettype none
`timescale 100fs/100fs
module VIOtest_viotest_viotest1
    ( // Inputs
      input wire  c$arg // clock
    , input wire  c$arg_0

      // Outputs
    , output wire [1:0] result
    );

  wire  probe_in0;
  (* KEEP = "true" *) wire [0:0] my_probe_out_0;
  wire  probe_out0;
  (* KEEP = "true" *) wire [0:0] my_probe_out_1;
  wire  probe_out1;
  (* KEEP = "true" *) wire [0:0] my_probe_in;
  assign probe_in0 = c$arg_0;

  assign probe_out0 = my_probe_out_0;
  assign probe_out1 = my_probe_out_1;
  assign my_probe_in = probe_in0;

  viotest_vioProbe_E5D466CB96E912F9 vio_inst
    ( .clk (c$arg)
    , .probe_in0 (my_probe_in)
    , .probe_out0 (my_probe_out_0)
    , .probe_out1 (my_probe_out_1) );

  assign result = {probe_out0,   probe_out1};

endmodule

Still TODO:

• [X] Write a changelog entry (see changelog/README.md)
• [X] Check copyright notices are up to date in edited files