clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler
https://clash-lang.org/
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Add reset-related convenience functions #2539

Closed martijnbastiaan closed 1 year ago

martijnbastiaan commented 1 year ago

Still TODO:

martijnbastiaan commented 1 year ago

@DigitalBrains1 @leonschoorl I've added proposal for the new constraint aliases. I'm reasonably happy with their names and definition (keep in mind the long-term plan is to get rid of KnownDomain except for things like resetGen and clockGen). I also think these two constraints will cover almost all cases, so I don't feel like it's necessary to add constraints for ActiveEdge and friends. Lastly, I'm not super-pleased with the __N.B.__ explanations right now, please make suggestions (unless you guys think it's clear enough!).

martijnbastiaan commented 1 year ago

Maybe HasSynchronousReset dom / SetsSynchronousReset dom? (Not a big fan of contracting it to Sync btw, we don't do that anywhere else we don't do that in that module.)

martijnbastiaan commented 1 year ago

I've picked HasX in the end. It's a pattern used in the Haskell ecosystem more often, and I feel it pretty much reads as this domain has X.

DigitalBrains1 commented 1 year ago

I'd like it if the documentation points out how users can manage these constraints efficiently. We discussed how people could create their own type synonyms in a single design with multiple clock domains like

type DesignDomain dom =
  ( HasSynchronousReset dom
  , HasDefinedInitialValues dom
  )

and then write all their domain-polymorphic functions in the design as

f ::
  DesignDomain dom =>
  Signal dom [...]

which is just as much code as KnownDomain dom, but correctly provides constraints whenever they use, say, orReset somewhere.