Add `Clash.Annotations.SynthesisAttributes.markDebug` (plus an unfortunate amount of baggage)

[martijnbastiaan]

I was playing around with constraint files and thought it would be nice if we could have a term level way of annotating signals with synthesis attributes. That is, the markDebug proposed in this PR. Unfortunately, I ran into quite a number of things I needed (and "needed") to fix before being able to add the function:

• Fixed a layout issue with block rendering in VHDL
• Discovered tests in shouldwork/ that weren't part of clash-testsuite
• Fixed an issue where VHDL would render a bool attribute, while only boolean is recognized
• Add TermLiteral (Vec n a)
• Refactored and simplified coreToAttrs / coreToAttr. The old implementation tried to be helpful with its error messages, but I didn't feel they helped out very much. Reading the code wasn't as nice as it could be either so...
• Generalized Attr to work over Symbol (type level) and String (term level)
  • Preparation work for annotate
• Removed Attr' now that Attr is generalized
• Add annotate: a way of adding synthesis attributes to signals
• Add markDebug: a convenience function that emits all keep/debug pragmas needed for synthesis tooling (currently verified for Vivado and Quartus)

Each of these points correspond to a commit. This PR can be split up into multiple smaller ones if desired.

Still TODO:

• [X] Write a changelog entry (see changelog/README.md)
• [X] Check copyright notices are up to date in edited files