clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler
https://clash-lang.org/
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VIO causes failure in `Clash.Netlist.BlackBox` #2549

Closed kleinreact closed 1 year ago

kleinreact commented 1 year ago

I get

GHC: Setting up GHC took: 0.374s
GHC: Compiling and loading modules took: 0.373s
Hint: interpreting "Clash.Cores.Xilinx.VIO.Internal.BlackBoxes.vioProbeBBF"
Hint: Interpreting Clash.Cores.Xilinx.VIO.Internal.BlackBoxes.vioProbeBBF
Clash: Parsing and compiling primitives took 0.605s
GHC+Clash: Loading modules cumulatively took 1.484s
Clash: Compiling Test.topEntity
Clash: Normalization took 0.014s

<no location info>: error:
    Other error:
    user error (Pattern match failure in 'do' block at src/Clash/Netlist/BlackBox.hs:1193:23-77)

for the following input

module Test where

import Clash.Prelude
import Clash.Cores.Xilinx.VIO

topEntity :: Clock System -> Signal System Bit
topEntity c = hwSeqX probe v
  where
    probe :: Signal System Bit -> Signal System ()
    probe = vioProbe ("v" :> Nil) Nil () c v

    v = pure high

when I run cabal run clash -- --verilog Test.hs on master.

(GHC is v9.2.8, clash-cores has been built with cabal build clash-cores first)

EDIT: same for GHC v9.0.2

christiaanb commented 1 year ago

Right, the failing code assumes that the functional arguments of primitives have exactly one output port. This assumption doesn't hold for:

christiaanb commented 11 months ago

We've released v1.8.0, which includes a fix for this issue.