Open christiaanb opened 1 year ago
I can't reproduce this using 9.6.2, did you mean to write 9.8? Or it could be an modelsim version difference, I've got
$ vsim -version
Model Technology ModelSim - INTEL FPGA STARTER EDITION vsim 2020.1 Simulator 2020.02 Feb 28 2020
$ cabal run clash-testsuite -- --no-vivado -p IntegralTB.SystemVerilog
.
tests
shouldwork
Numbers
IntegralTB
SystemVerilog
clash (gen): OK (20.75s)
tools
ModelSim
vlib testBench: OK (0.04s)
vlog testBench: OK (0.15s)
sim testBench: OK (0.28s)
If I counted the bits right, in your case there is something wrong with the SystemVerilog implementations of div @Int8
and div @Int16
, they're producing x
s as a result.
But interestingly others like for Int32
, Int64
or Int
are all ok.
On
master
, using GHC 9.6.2, I'm seeing: