clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler
https://clash-lang.org/
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`convertReset`: always filter synchronous source #2573

Closed DigitalBrains1 closed 1 year ago

DigitalBrains1 commented 1 year ago

PR #2553 already inserted a flip-flop to filter source glitches if the target was asynchronous, but this is incomplete. The problem exists for both asynchronous and synchronous target domains. Any source glitches can actually unintendedly end up in the dual flip-flop synchronizer of a synchronous target as well.

Still TODO: