clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler
https://clash-lang.org/
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Fix `alteraPll` `qsys` generation #2587

Closed DigitalBrains1 closed 1 year ago

DigitalBrains1 commented 1 year ago

PR #2417 caused a bug in the generation of the qsys file: it generated a spurious extra output clock which was completely unused otherwise.

Still TODO: