clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler
https://clash-lang.org/
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Fix `alteraPll` `qsys` generation (copy #2587) #2588

Closed mergify[bot] closed 9 months ago

mergify[bot] commented 9 months ago

This is an automatic copy of pull request #2587 done by Mergify. Cherry-pick of 5b055fb3fcdaf6e2b89cb86486d7280fc781fa84 has failed:

On branch mergify/copy/1.6/pr-2587
Your branch is up to date with 'origin/1.6'.

You are currently cherry-picking commit 5b055fb3f.
  (fix conflicts and run "git cherry-pick --continue")
  (use "git cherry-pick --skip" to skip this patch)
  (use "git cherry-pick --abort" to cancel the cherry-pick operation)

Changes to be committed:
    new file:   changelog/2023-10-05T16_56_51+02_00_correct_qsys

Unmerged paths:
  (use "git add <file>..." to mark resolution)
    both modified:   clash-lib/src/Clash/Primitives/Intel/ClockGen.hs

To fix up this pull request, you can check it out locally. See documentation: https://docs.github.com/en/github/collaborating-with-pull-requests/reviewing-changes-in-pull-requests/checking-out-pull-requests-locally


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