Closed DigitalBrains1 closed 5 months ago
This issue prevents me from writing the code I want to write in the examples in #2592 (I need to add type signatures where they aren't needed).
When run with -fclash-debug DebugSilent
or higher you can see it stumble over the type of the enable signal a little earlier:
Clash.Normalize(212): Expr belonging to bndr: enableGen (:: Enable
(ErrOnConflict
(Signal "System" Bit -> Signal "System" Bit)
(Merge' (Found "System") (TryDomain (Signal "System" Bit -> Signal "System" Bit) (Signal "System" Bit))))) has a non-representable return type. Not normalising:
(Λdom ->
Enable @dom (clockGen1[GlobalId] @dom))
@(ErrOnConflict
(Signal "System" Bit -> Signal "System" Bit)
(Merge' (Found "System") (TryDomain (Signal "System" Bit -> Signal "System" Bit) (Signal "System" Bit))))
Some alternative workarounds you might like better:
exposeClockResetEnable (register 0 dIn) clk rst en
withClockResetEnable clk rst en (register 0 dIn)
Oh, such a register 0 dIn
workaround is much smoother, thanks!
In Clash
master
and1.6
, there is a bug when generating HDL under very specific conditions. Only with GHC 9.0.2 (out of the versions we test in CI), with multiple hidden enabled, an annotation fromClash.Annotations.SynthesisAttributes
and the following reproducer:VHDL generation will produce the error:
Verilog and SystemVerilog instead say:
Each of the following is enough to make the code produce HDL again:
Annotate
clk
,rst
oren
exposeClockResetEnable
topEntity
(topEntity = exposeClockResetEnable ...
)Type-applying
register
, though, does not help.I created a branch issue-2593 which tests the reproducer in CI. The full file with the reproducer is T2593.hs For 1.6, the branch is issue-2593-1.6.