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clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler
https://clash-lang.org/
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Prepare for Clash 1.8 release #2600

Closed christiaanb closed 8 months ago

DigitalBrains1 commented 8 months ago

I've fixed some formatting in the Changelog. I'd rather not do it in the GitHub interface, it's rather cumbersome. Instead, I hope you'd be happy with a diff instead

```diff diff --git a/CHANGELOG.md b/CHANGELOG.md index 988a6fc34..e8ed5f0ee 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,7 +6,7 @@ Some remarkable changes for this release: * Support for GHC 9.2, 9.4, 9.6 and 9.8. Clash now supports GHC versions 8.6 through 9.8. * Major overhaul of the clocking functionality in `Clash.Xilinx.ClockGen` and `Clash.Intel.ClockGen`, see their respective entries below -* `mealyS` function (and several variations) to make writing state machines using the strict State monad easier +* `mealyS` function (and several variations) to make writing state machines using the strict `State` monad easier * Overhaul of `resetGlitchFilter`, see its respective entries below. * A new clock type `DiffClock` is introduced to make it more convenient to interact with differential clock signals. @@ -35,7 +35,7 @@ Added: * `Clash.Annotations.SynthesisAttributes.markDebug`: a way of marking a signals "debug", instructing synthesizers to leave the signal alone and offer debug features * Add hex and octal BitVector parsing. [#1772](https://github.com/clash-lang/clash-compiler/pull/2505) * `1 <= n => Foldable1 (Vec n)` instance (`base-4.18+` only) -* You can now use ~PERIOD, ~ISSYNC, ~ISINITDEFINED and ~ACTIVEEDGE on arguments of type Clock,Reset,Enable,ClockN and DiffClock. +* You can now use `~PERIOD`, `~ISSYNC`, `~ISINITDEFINED` and `~ACTIVEEDGE` on arguments of type `Clock`,`Reset`,`Enable`,`ClockN` and `DiffClock`. Removed: @@ -56,10 +56,10 @@ Changed: * There are new functions `unsafeClockWizard` and `unsafeClockWizardDifferential` for advanced use cases which directly expose the `locked` output of the wizard. * All clock generators now have the option to output multiple clocks from a single instance. * `clockWizardDifferential` now gets its input clock as a `DiffClock` type; use `clockToDiffClock` to generate this in your test bench if needed. Previously, the function received two clock inputs, but this generated `create_clock` statements in the top-level SDC file for both phases which is incorrect. - * A constraint was removed: The /output/ clock domain no longer requires asynchronous resets. This was originally intended to signal that the outgoing lock signal is an asynchronous signal. The constraint does not convey this information at all and is wrong; it also prevents using synchronous resets in the circuit as recommended by Xilinx. Note that if you use the `unsafe` functions, it is still necessary to synchronize the `locked` output in your design. + * A constraint was removed: The _output_ clock domain no longer requires asynchronous resets. This was originally intended to signal that the outgoing lock signal is an asynchronous signal. The constraint does not convey this information at all and is wrong; it also prevents using synchronous resets in the circuit as recommended by Xilinx. Note that if you use the `unsafe` functions, it is still necessary to synchronize the `locked` output in your design. * The port names of the primitives in HDL are now correctly lower case. * Add Tcl generation. This moves the responsibility of MMCM component generation from the user to `clashConnector.tcl`, which can be found in [`clash-lib:Clash.DataFiles`](https://hackage.haskell.org/package/clash-lib-1.8.0/docs/Clash-DataFiles.html). - * The wizards now use the user-provided name as the name of the /instance/ rather than the name of the /IP core/. This change was also done for `Clash.Intel.ClockGen` in Clash v1.2.0 in March 2020, when Clash started generating Intel Qsys files. Before that, the user needed to generate a Qsys component manually. Now, in Clash v1.8.0, we also generate the Tcl for Xilinx wizards. When the user is responsible for creating the IP core, it makes sense to always set the component name to the user-provided value. But when that is also generated by Clash, that is no longer needed. Allowing users to set the instance name instead makes it possible to match on the instance in SDC files and such. + * The wizards now use the user-provided name as the name of the _instance_ rather than the name of the _IP core_. This change was also done for `Clash.Intel.ClockGen` in Clash v1.2.0 in March 2020, when Clash started generating Intel Qsys files. Before that, the user needed to generate a Qsys component manually. Now, in Clash v1.8.0, we also generate the Tcl for Xilinx wizards. When the user is responsible for creating the IP core, it makes sense to always set the component name to the user-provided value. But when that is also generated by Clash, that is no longer needed. Allowing users to set the instance name instead makes it possible to match on the instance in SDC files and such. * The IP core generators in `Clash.Intel.ClockGen` now declare that their input domain needs to have asynchronous resets (`HasAsynchronousReset`), as the functions react asynchronously to their reset input and thus need to be glitch-free. The functions marked `unsafe` do not have this constraint; instead, the function documentation calls attention to the requirement. * `resetGlitchFilter` now uses a counter instead of shift register, allowing glitch filtering over much larger periods. * `resetGlitchFilter` now filters glitches symmetrically, only deasserting the reset after the incoming reset has stabilized. For more information, read [#2374](https://github.com/clash-lang/clash-compiler/pull/2374). @@ -67,7 +67,7 @@ Changed: * `fromJustX` now uses `deepErrorX` instead of `errorX`. This adds `NFDataX` constraints to `blockRam` like functions, `asyncRam` and `writeToBiSignal`. [#2113](https://github.com/clash-lang/clash-compiler/pull/2113) * All memory functions now use `deepErrorX` for `XException`s. This adds `NFDataX` constraints to `asyncRom`, `asyncRomPow2` and `asyncRom#`. [#2113](https://github.com/clash-lang/clash-compiler/pull/2113) * Before this release, `scanl1` was re-exported from the Haskell Prelude. Clash's Prelude now exports a `Vec` specialized version. -* When generating (System)Verilog, Clash now sets the default net type to none. This means any implicitly declared signal in the design will trigger an error when elaborating the design. +* When generating (System)Verilog, Clash now sets the default net type to `none`. This means any implicitly declared signal in the design will trigger an error when elaborating the design. * Blackbox templates no longer have the `outputReg` key, it has been replaced with the more general `outputUsage` which specifies how signals are used in terms of whether writes are * continuous (i.e. a concurrent context) @@ -126,16 +126,16 @@ Internal changes: * Black box functions declare their usage, necessary for implicit netlist usage analysis implemented in [#2230](https://github.com/clash-lang/clash-compiler/pull/2230) * Added `showsTypePrec` to `TermLiteral` to make `TermLiteral SNat` work as expected. Deriving an instance is now a bit simpler. Instances which previously had to be defined as: -```haskell -instance TermLiteral Bool where - termToData = $(deriveTermToData ''Bool) -``` + ```haskell + instance TermLiteral Bool where + termToData = $(deriveTermToData ''Bool) + ``` -can now be defined using: + can now be defined using: -```haskell -deriveTermLiteral ''Bool -``` + ```haskell + deriveTermLiteral ''Bool + ``` ## 1.6.6 *Oct 2nd 2023* ```
christiaanb commented 8 months ago

I've fixed some formatting in the Changelog. I'd rather not do it in the GitHub interface, it's rather cumbersome. Instead, I hope you'd be happy with a diff instead

Thanks. I've included your fixes. I've also added links to pull requests where there wasn't already an issue or PR to identity the line in the changelog.