Produced VHDL cannot be used within Vivado block designs

[bgamari]

It turns out that Vivado's block design facility has the annoyingly arbitrary limitation that ports may only be of type std_logic or std_logic_vector. Unfortunately, this means that VHDL produced by Clash, which contains various types, cannot be used in this facility.

It would be great if there were a way to flatten ports to std_logic[_vector] to side-step this limitation.

[DigitalBrains1]

I know we turn a bunch of things into std_logic_vector if you give flag -fclash-hdlsyn Vivado to clash but I forgot the details. Do you already specify that flag when you observe the problem?

If that flag doesn't do the job, would a flag that turns all ports of the topEntity into std_logic{,_vector} fit the bill or perhaps on all entities with a Synthesize annotation?

[edit] Perhaps add -fclash-no-render-enums as well (which appears to be missing from the documentation) [/edit]

[bgamari]

Indeed I observe the issue with -fclash-hdlsyn Vivado. Sadly -fclash-no-render-enums also does not appear to help.

In all cases I see things like: clk : in wombat_types.clk_System; and s_axi_awvalid : in wombat_types.index_2

[martijnbastiaan]

A workaround would be to translate to Verilog instead. Whether this is usable entirely depends on your situation of course.