Open martijnbastiaan opened 4 months ago
(Port @"foo" ...)
And then you can go one step further and use a typeclass to name ports that contain multiple signals. This way you can do Port @"some_dataflow" x
and get names for "some_dataflow_valid"
, "some_dataflow_ready"
and "some_dataflow_dat"
(for example). This is also useful for top level/synthesis units. :smile:
I've got this beauty:
I feel this it is now very error prone to add a probe, as I cannot easily see which probe name matches to which signal. We should use an
inst
like invocation: