Verilog fromEnum doesn't sign extend properly

[basile-henry]

It looks like #2689 solved some related problems (Signed.fromInteger#), but I think there are still a few issues doing proper sign extension in other primitives.

To reproduce:

import Clash.Prelude

topEntity :: Signed 8 -> Int
topEntity = fromEnum

Which produces (in clash 1.4.7, which we're still using :cry: ):

/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.
** GENERATED BY CLASH 1.4.7. DO NOT MODIFY.
*/
`timescale 100fs/100fs
module topEntity
    ( // Inputs
      input signed [7:0] x

      // Outputs
    , output wire signed [63:0] result
    );
  // Test.hs:4:1-9
  wire signed [63:0] wild;
  // Test.hs:4:1-9
  wire signed [63:0] c$wild_app_arg;

  assign wild = $signed(c$wild_app_arg);

  assign result = wild;

  assign c$wild_app_arg = $signed({{(64-8) {1'b0}},x});

endmodule

And in clash 1.9.0 (commit e6522d73be):

/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.
** GENERATED BY CLASH 1.9.0. DO NOT MODIFY.
*/
`default_nettype none
`timescale 100fs/100fs
module topEntity
    ( // Inputs
      input wire signed [7:0] c$arg

      // Outputs
    , output wire signed [63:0] result
    );

  assign result = $signed({{(64-8) {1'b0}},c$arg});

endmodule